Delay locked loop circuitry for clock delay adjustment

ABSTRACT

Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to clock delay adjustmentcircuitry. In particular, the present invention relates to thegeneration of a set of phase vectors and the generation of output clocksthat have precise phase relationships to an input clock.

[0002] Previous art includes Rambus patent, U.S. Pat. No. 5,485,490,Leung and Horowitz, which discloses two independent loops, the first ofwhich creates a fixed number of phase vectors, the second of whichcreates an output clock that is in phase with the input clock. Alsodisclosed in this patent is the use of separate circuitry to create aleading phase clock to the output clock by selecting a pair of phasevectors and interpolating between them to produce an output that leadsthe output clock by the delay between phase vectors available from thefirst loop.

[0003] IEEE Journal of Solid-State Circuits, Vol. 29, No. 12, December1994, Lee, et.al. (“Lee”) discloses a pair of delay-locked loops (DLL)for transmitting and receiving data in DRAMs. IEEE Journal ofSolid-State Circuits, Vol. 31, No. 4, April 1996, Tan,pi et.al. shows atwo-loop architecture in which an frequency locked-loop (FLL) isdesigned to lock onto an external input frequency and to control the DLLfor lock-in to the phase of the external input clock.

[0004] It is desirable to improve on the generation of a leading outputclock to the in phase output clock. There are several drawbacks to theinvention disclosed in U.S. Pat. No. 5,485,490. Phase locked loopcircuitry employing a VCO and single order loop filter to create phasevectors is a second order system. This second order system has stabilityproblems associated with its operation. Furthermore, the VCO phase lockloop accumulates phase error in response to sudden change in phase oninputs to the loop, where the input includes not only the input clockbut also the power supplies to the loop. This occurs because the loopchanges the frequency of the VCO in response to a sudden phase changeand this frequency shift is integrated to become phase error whichpersists for a time on the order of the reciprocal loop bandwidth. (SeeLee, above). This causes the loop to be noise sensitive when the noiseis in the form of sudden phase shifts. Another drawback regarding theprior art patent is that the subloop used for generating the in-phaseclock relies on the accuracy and similarity of a second phaseinterpolator (out-of-phase phase interpolator) to produce the leadingclock. Any lack of matching between the out-of-phase phase interpolatorand the in-phase phase interpolator will create a phase error in thedesired phase relationship between the leading clock and the in-phaseclock. Another drawback concerns the acquisition time of the VCO whichcan be quite long after restoration of a lost input clock, depending onhow long the input clock has been absent.

SUMMARY OF THE INVENTION

[0005] The present invention provides delay locked loop circuitry forgenerating a predetermined phase relationship between a pair of clocks.A first delay-locked loop (DLL) includes delay elements arranged in achain, the chain receiving an input clock and generating, from the delayelements, a set of,phase vectors, each shifted a unit delay from theadjacent vector. The first delay-locked loop adjusts the unit delays inthe delay chain using a delay adjustment signal so that the phasevectors span a predetermined phase shift of the input clock.

[0006] In a preferred embodiment, a second DLL is used, although thesecond DLL could be used with another circuit which produces twodifferent delayed clock signals. The second DLL selects, from the firstDLL, a pair of phase vectors which brackets the phase of an input clock.A phase interpolator receives the selected pair of vectors and generatesan output clock and a delayed output clock, the amount of the delaybeing controlled by the delay adjustment signal of the firstdelay-locked loop circuitry.

[0007] Preferably, a phase detector in the second DLL compares thedelayed output clock with the input clock and adjusts the phaseinterpolator, based on the phase comparison, so that the phase of thedelayed output clock is in phase with the input clock. The phaseinterpolator is preferably adjusted with a control circuit including adigital memory for storing a count corresponding to the delayadjustment, which can be maintained in the absence of the input clocksignal.

[0008] Preferably, the first DLL includes a control circuit with adigital memory for providing the desired delay adjustment to theadjustable delay elements. A filter is used between the phase detectorand the control circuit to reduce loop jitter.

[0009] The present invention is advantageously used for the transmit andreceive clocks in high speed DRAM and a high speed DRAM bus channel.

[0010] Other objects, features, and advantages of the present inventionwill be apparent from the accompanying drawings and from the detaileddescription which follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The features and advantages of the present invention areillustrated by way of example and are by no means intended to limit thescope of the present invention to the particular embodiments shown, andin which:

[0012]FIG. 1 shows a block diagram of a delay locked loop for generatingphase vectors, K<r:0>;

[0013]FIG. 2 shows a more detailed block diagram than FIG. 1 of adelayed locked loop for generating phase vectors, K<r:0>, according toone embodiment;

[0014]FIG. 3 shows a more detailed architecture than FIG. 2 of a delayedlocked loop for generating phase vectors, K<r:0>, according to oneembodiment;

[0015]FIG. 4 shows another embodiment of a delay locked loop forgenerating phase vectors using buffered delay elements and a bufferclock source.

[0016]FIG. 5 shows a block diagram of the architecture of a DLL forgenerating an Output Clock in precise phase relationship with an InputClock according to one embodiment;

[0017]FIG. 6 shows a more detailed architecture than FIG. 5 of a DLL forgenerating an-Output Clock in precise phase relationship with an Inputclock according to one embodiment;

[0018]FIG. 7 shows another embodiment of a DLL for generating an OutputClock in precise phase relationship with an Input Clock using anadjustable delay section in the path of both the Output clock and thefeedback clock;

[0019]FIG. 8 shows another embodiment of an adjustable delay sectionhaving one adjustable delay for use in FIG. 7;

[0020]FIG. 9 shows another embodiment of an adjustable delay sectionhaving at least two adjustable delays for use in FIG. 7;

[0021]FIG. 10 shows an embodiment for producing a pair of delays fromthe same chain for use in FIG. 7;

[0022]FIG. 11 shows a set of four phase vectors each separated by a 90degree interval and spanning 360 degrees shift of the 0 degree vector;

[0023]FIG. 12 shows a set of eight phase vectors each separated by a 45degree interval and spanning 360 degrees shift of the 0 degree vector;

[0024]FIG. 13 shows a set of 12 phase vectors each separated by a 30degree interval and spanning 360 degrees shift of the 0 degree vector;

[0025]FIG. 14 shows a set of four phase vectors each separated by a 90degree interval and spanning 360 degrees shift of the 0 degree vector,with the Input Clock and feedback clock between the 90 and 180 degreephase vectors and the Output Clock between the 0 and 90 degree vectorsand 90 degrees earlier in time than the input clock;

[0026]FIG. 15 depicts a case in which the input clock is between the 135and 180 degree phase vectors, with the initially selected phase vectorsbeing the 0 and 45 degree vectors;

[0027]FIG. 16A shows an embodiment of a delay element for use in a delaylocked loop;

[0028]FIG. 16B shows another embodiment of a delay element for use in adelay locked loop;

[0029]FIG. 17 shows an embodiment of a digital to analog converter foruse in a delay locked loop;

[0030]FIG. 18 shows an embodiment of a phase interpolator for use in adelay locked loop; and FIG. 19A and 19B show an embodiment of a dutycycle correcting amplifier for use in a delay locked loop. FIG. 19A isthe amplifier in which the duty cycle is corrected and FIG. 19B is theduty cycle error detecting circuit which applies a correction signal tothe amplifier in FIG. 19A.

[0031]FIG. 20 is a block diagram of a TrimAdj circuit for use in onevariation of the embodiment of FIG. 7.

[0032]FIG. 21 is a circuit diagram of one embodiment of a phase detectoras set forth in FIG. 6.

[0033]FIG. 22 is a block diagram of a DRAM system incorporating thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0034] Embodiments of the present invention provide a method andcircuitry to generate a set of phase vectors in a way that is moreimmune to noise on loop inputs including the power supplies, leading toa more stable set of phase vectors. Also, an output clock that has apredetermined phase relationship with an input clock is provided. Theeffect of clock buffer delays between the input clock and output clockis minimized. The delay of an adjustable delay element is adjusted witha counter and a digital to analog converter, the count in the counterdigitally representing the current delay adjustment of the delay lockedloop. The digital count is converted to a signal suitable for adjustingan adjustable delay element used in a delay locked loop.

[0035] The setting of current delay adjustment of the loop is digitallyrepresented so that the setting may be stored while the loop is in apowered-down or low power state. There is quick re-acquisition of thelocked state of a delay locked loop after the delay locked loop has beenpowered down.

[0036] In one embodiment of the present invention a delay locked loop(DLL) is employed for generating phase vectors. Referring to FIG. 1, theDLL 100 receives an external clock, ClkSrc 101, and generates phasevectors, K<r:0> 103. A convenient way to represent the set of phasevectors for a periodic signal is to draw the vectors in phase space asin FIG. 11. In this figure there are four vectors each spaced apart by90 degrees and spanning a 360 degree phase shift of the 0 degree vector.Each vector in this figure represents a time delay of one fourth of thecycle of the periodic signal. FIGS. 12 and 13 show alternate sets ofphase vectors. FIG. 12 shows a set of vectors spaced at 45 degreeintervals and spanning a 360 degree phase shift of the 0 degree vector.FIG. 13 shows a set of vectors spaced at 30 degree intervals andspanning s 360 degree phase shift of the 0 degree vector.

[0037] Referring to the embodiment shown in FIG. 2, the DLL 100 is afirst order loop comprising a set of adjustable delay section 110, acontrol circuit 120 and a phase detector 130. The phase detector 130receives the external clock, ClkSrc 150 from which it derives a clockinput ClkIn (not shown), a set of phase vector lines 140 and the lastphase vector K<r> on line 160. The output of phase detector 130 iscoupled to the control circuit 120 which processes the output of thephase detector to generate a delay adjust signal 125 for adjusting thedelay of the delay elements. The adjustable delay elements are adjustedso that the phase of K<r> is the same as the clock input, ClkIn.

[0038]FIG. 3 shows an embodiment of the DLL in more detail. Inparticular, adjustable delay section 205 comprise a set of fouridentical adjustable delay elements 210 connected in series with theoutput of each delay element 210 except the last element connected tothe input of the next element 210. While four delay elements are shownin the particular embodiment, any number such as two, three, four, six,eight or twelve, can be used. This arrangement produces a set of clocks,called phase vectors K<r:0> 270, each shifted in time from the next by adelay, called a unit delay, generated by the adjustable delay section205. Each adjustable delay element 210 receives the delay adjust signalDlyAdj 260 from control circuit 230, comprising counter control circuit240 and digital to analog converter (DAC) 250. Counter control circuit240 receives an input, PhDiff 225, from phase detector 220 and generatescount Cnt<c:0> 245 for input to the DAC. In one embodiment, controlcircuit 230 is implemented with digital circuits to permit the storageof the current delay adjustment setting of the loop, held by Cnt<c:0>245, during times when the ClkSrc 200 is not present, perhaps during aperiod when the system is shut down to save power. The saved settingpermits the loop to quickly re-acquire a locked condition when theClkSrc is reactivated.

[0039] Continuing with FIG. 3, phase detector 220 receives as inputsClkIn 215 derived from the ClkSrc 200 via buffer 202 and the last phasevector K<r> 280. In another embodiment, buffer 202 performs duty cyclecorrection as well as amplification to assure that ClkIn 215 has a 50%duty cycle. Duty cycle correction is discussed in greater detail below.

[0040] In FIG. 3, adjustable delay element 210 may be implementedaccording to the embodiment shown in FIG. 16A, which shows a delayelement 1010 and a bias circuit 1000. In FIG. 16A the delay element is adifferential delay element, having both true and complementary inputsand outputs. The circuit operates to delay the differential inputs IN1005 and IN_B 1015 to produce delayed outputs Out 1130 and Out_B 1140.The amount of delay is adjusted by adjustable current source 1020, whichcontrols the amount of current switched by differential pair 1100 and1110. The greater the amount of current switched the smaller delayproduced by the differential pair. Transistors 1080 and 1090 act asclamps to limit the swing of the differential pair allowing small delaysto be realized by the circuit.

[0041] The adjustable delay element may also be implemented according tothe embodiment shown in FIG. 16B. In this figure section 1215 functionsas a fixed delay comprising a current source 1260 and a differentialpair 1220 and 1230, and section 1225 operates as a phase interpolatorcomprising differential pair 1330 and 1340 with current source 1320 anddifferential pair 1290 and 1300 with current source 1310 to produce adelay that is adjustable between a stage delay to a fixed delay plus thestage delay. The stage delay represents the fixed delay time through theinterpolator stage 1225. The phase interpolator delay stage 1225 isadjusted by varying the current sources Ix 1320 and Iy 1310. If Ix is atmaximum and Iy is turned off the output signals Out 1380 and Out_B 1370are produced by transistors 1330 and 1340 in phase with the inputsignals but delayed by the stage delay. If Iy 1310 is maximum and Ix1320 is off then the output signals Out 1380 and Out_B 1370 are producedby transistors 1290 and 1300 and are delayed by amount of the fixeddelay provided by the 1215 section plus the stage delay. Therefore, thephase interpolator delay stage 1225 is adjustable through a range ofdelay equal to the fixed delay of the 1215 section.

[0042]FIG. 3 depicts a DAC which may be implemented according to the DACshown in FIG. 17, which depicts a circuit for converting a digital countCntcc:0> 1510 and its complement Cnt_B<c:0> 1500 to a differentialcurrent pair, Ictl 1640 and Ictl_B 1590 proportional to the count. FIG.17 shows three sections of circuitry, a set of binary weighted currentsources 1520, a set of switches 1540 for producing the true currentoutput Ictl 1640 and a set of switches 1530 for producing the complementoutput Ictl_B 1590. If the count input Cnt<c:0> 1510 is all ones thenIctl 1640 has a maximum current, Max_I, which is the sum of all of thecurrent sources 1650, 1660, 1670 through 1680 and the complementarycurrent Ictl_B is zero. If the count input Cnt<c:0> 1510 is all zerosthen Ictl_B 1590 has the maximum current, Max I, and Ictl is zero.Intermediate counts produce intermediate amounts of current, Im, and(Max_I-Im) on Ictl and Ictl_B respectively. This DAC is suitable forcontrolling the differential input delay adjust signals of theadjustable delay element 210 shown in FIG. 16B for the delay locked loopshown in FIG. 3.

[0043] The system shown in FIG. 3 operates as follows. Phase detector220 compares the ClkIn signal, with the last phase vector K<r> 280 todetermine the phase difference from a predetermined phaserelationship-between the two clocks. In one embodiment the predeterminedphase difference could be zero degrees. In another embodiment thepredetermined phase difference could be 180 degrees. The phasedifference is represented by signal PhDiff 225. Counter control blockthen converts the PhDiff signal into a digital count, Cntcc:0> 245, andDAC 250 converts the count value into an analog quantity, DlyAdj 260,for adjusting the adjustable delay elements. In some embodiments theCnt<c:0> signal and the DlyAdj signal may be differential signals. Thedelay adjustment operates to change the delay of the adjustable delayelements so that the phase difference from the predetermined phaserelationship between clock input, ClkIn and K<r> is made close to zero.When this condition occurs the DLL is locked, and each adjustable delayelement has substantially the same delay. Thus each phase vector isdisplaced in time from the adjacent vector by an amount equal to thesetting of the adjustable delay element. This time displacement istermed a unit delay. The result is that the phase vectors span a 360degree phase shift of the ClkIn signal 215. These phase vectors can nowbe used in another DLL to lock the phase of an output clock in precisephase relationship to the arbitrary phase of an input clock.

[0044] For FIG. 3, an alternate embodiment could use fewer delayelements to produce phase vectors that span the 360 degree phase shiftof the ClkIn if each delay element, such as the ones depicted in FIGS.16A and 16B, can produce both true and complementary outputs. Forexample, instead of using four delay elements each separated by 90degrees, two delay elements separated by 90 degrees could be used if thedelay element had true outputs yielding delays of 90 and 180 degrees andcomplementary outputs yielding 270 and 360 degrees, respectively.Alternatively, fewer delay elements could be used if the phase detectorwere designed to detect phase differences from a predetermined phaserelationship of 180 degrees. Using such a phase detector would onlyrequire that two delay elements be used spanning a 180 degree phaseshift of the ClkIn signal. The outputs of the delay elements could beinverted in a separate circuit which receives the phase vectors, so thata set of phase vectors spanning 360 degrees is obtained. For embodimentsin which the phase shift of the ClkIn signal spans only 180 degreesbuffer 202 may perform a duty cycle correction function to assure thatthe ClkIn signal 215 has a 50% duty cycle. This is especially importantwhen the remaining span of 180 degrees is derived through inversion ofthe phase vectors spanning the first 180 degrees, because inversion willnot generate the proper phase shift if the duty cycle is notsubstantially close to 50%.

[0045] Referring the embodiment in FIG. 4, an additional adjustabledelay element has been placed in the circuit to receive the last phasevector. This additional delay has the effect of insuring that each phasevector has the identical loading as the other phase vectors, so thatphase errors caused by loading differences are substantially eliminated.Rather than connecting the delay adjust signal 265 to the DlyAdj signal260, signal 265 may be connected to a convenient voltage, because theoutput of the additional delay is not used. This eliminates some of theloading on the DlyAdj signal 260.

[0046] Continuing with the embodiment of FIG. 4, phase vectors 275 arebuffered by buffers 212 in order to further control the loading on thevectors by isolating the loading of the phase vectors from othercircuits which may receive the vectors. A buffered version of ClkIn 215and a buffered version of the last phase vector Kcr> 285 are sent to thephase detector. This guarantees that buffered version of the phasevectors K<r:0> 275 are separated in phase by a unit delay and that theset of buffered phase vectors span a 360 degree or 180 degree shift ofthe buffered ClkIn signal depending upon the embodiment chosen.

[0047] Also shown in FIG. 4 is a version of buffer 202 which has a dutycycle correcting circuit 290 attached. The duty cycle correcting circuit290 senses signal 214 for a deviation from a 50% duty cycle. It thenfeeds a correction signal to buffer 202 to correct signal 214. In someembodiments signal 214 is a differential signal and the error signal 295is a differential signal.

[0048] An embodiment of a duty cycle correcting amplifier is shown inFIGS. 19A and 19B. FIG. 19A shows the correcting stage 2005 and thebuffering stage 2055 and FIG. 19B shows the duty cycle error detectingstage 2215. In FIG. 19A differential pair 1960 and 1970 receive theinput clock differential on In+ 1920 and In− 1930 and produce adifferential output clock on Corr Clock_B 2090 and Corr Clock 2100. Ifthe duty cycle deviates from 50% then the circuit shown in FIG. 19B willproduce a differential error voltage signal pair Error+ 2300 and Error−2200 from the differential pair 2230 and 2250 and capacitor 2260 actingas an integrator. Transistors 2220, 2280, 2290 and 2270 function as aload element especially suited for controlling the charge leakage acrossintegrating capacitor 2260. The differential error voltage signal pairis fed back to the correcting stage 2005 such that the duty cycle errorin the Corr Clock and Corr Clock_B signals is reduced by alteringcurrents 2110 and 2120 depending on the polarity of the error. Thus, theoutput of the buffering stage 2055 is a clock having a duty cyclesubstantially close to 50%.

[0049] In FIG. 4, as in FIG. 3, Phase detector 220 compares the ClkInsignal, with the last phase vector K<r> 280 to determine the phasedifference from a predetermined phase relationship between the twoclocks, and signal PhDiff 225 represents that difference. In FIG. 3,PhDiff signal 225 contains random variations due to the instantaneousphase error which, when used directly by Counter Control 240, causes anamount of overall loop jitter, thus affecting the stability of the phasevectors. In FIG. 4, the amount of jitter is reduced by filtering thePhDiff signal before converting it to DlyAdj signal 260. Shown in FIG. 4is an embodiment in which control circuit 230 includes filter 235 inaddition to counter control 240 and digital to analog converter (DAC)250. Filter circuit 235 receives an input, PhDiff 225, from phasedetector 220 and CntClk 241 from buffer 238 and generates output PhDiffF237 for input to the Counter Control 240, which receives CntClk 241 andgenerates count Cnt<c:0> 245 for input to DAC 250. In an embodiment inwhich the PhDiff signal is a digital signal, a digital filter is used,but either analog or digital filtering may be employed. CntClk 241operates the circuitry in both Filter 235 and Counter Control 240.Buffer 238 is employed when ClkSrc is a small swing signal but CounterControl 240 and Filter 235 require a full swing signal.

[0050] Types of digital filters that can be employed to reduce loopjitter include a majority-detector filter or an unanimity-detectorfilter. In either filter type, CntClk 241 operates circuitry whichsamples and stores the state, either true or false, of PhDiff 225. Amajority-detector filter saves the last N samples, where N is an oddnumber, of PhDiff signal 225 and determines whether a majority of thelast N cycles, say 3 out of 5 (N), are the same. If so, then themajority-detector filter activates PhDiffF 237 to alter the count incounter control 240. This type of filter alters the count in countercontrol 240 on every sample because there is always a majority of trueor false samples. An unanimity-detector filter also records the last Nsamples, where N can be even or odd, of the PhDiff signal but insteaddetermines whether all N cycles are the same. If all samples are thesame, the unanimity-detector filter activates the PhDiffF signal 237 toalter the count and at times during which not all the samples are thesame, the PhDiffF signal will not be activated to alter the count. Bothtypes of filters have the effect of reducing loop jitter, and eithertype may be used.

[0051] Turning now to FIG. 5, a pair of delay locked loops is depictedfor generating an output clock having predetermined phase relationshipto an input clock. The first delay locked loop 320 is one whichgenerates phase vectors K<r:0> 330 from a clock source ClkSrc 300 asdescribed above. The phase vectors and the DlyAdj signal 340 are thenused by a second delay locked loop 350 to create a precise phaserelationship between Input Clock 310 and Output Clock 360.

[0052]FIG. 6 shows an embodiment of the loop of FIG. 5 in more detail.First loop 400 is the phase vector loop which receives ClkSrc 410 andgenerates phase vectors K<r:0> 430 and DlyAdj signal 440. The secondloop 500 is the loop for creating the phase relationship between theInput Clock 650 and Output Clk 640. Loop 500 comprises a selectioncircuitry 510, phase interpolator 560, adjustable delay section 610which represents an integer multiple of adjustable delay elements, ClockBuffers 620 and 630, control circuit 570 and phase detector 590.

[0053] In FIG. 6, selection circuitry 510 receives the phase vectors 430and passes along a selected pair of vectors Kx 520 ad Ky 530, which arereceived by phase interpolator 560. The phase interpolator generates aninterpolated output clock 615 which is buffered by clock buffer 620 tobecome the Output Clock 640.

[0054] Adjustable delay section 610 also receives output clock 615 andfeeds the delayed clock to clock buffer 630 to generate FdBkClk 600.Control circuit generates PhAdj signal 550 for controlling theinterpolator 560. Control circuit 570 receives phase differenceinformation, PhDiff 580, from phase detector 590, which detects thedifference in phase between the Input Clk 650 and FdBkClk 600. Asdescribed previously, control circuit 570 may comprise counter control240 and DAC 250 such as in FIG. 3, to enable the saving of the settingof the current phase adjustment of the loop or Filter 235, CounterControl 240 and DAC 250 as in FIG. 4 to additionally reduce loop jitter.

[0055] Selection circuitry 510 may be implemented as an analog ordigital set of switches comprising a multiplexer, depending upon whetherthe phase vectors are low swing or full swing signals. Phaseinterpolator 560 may be implemented as shown in FIG. 18. Alternately,selection circuitry 510 may be merged or combined with interpolator 560,shown in FIG. 6 as block 562. In some embodiments when selectioncircuitry is combined with the phase interpolator, the circuit shown inFIG. 18 is duplicated several times, each duplicate connected to adifferent set of switches for applying a particular phase vector to theinterpolator.

[0056] The operation of the circuit of FIG. 18 is substantially similarto the circuit shown in FIG. 16B. Differential pair 1800 and 1810receive one of the selected phase vectors Kx 1700 and Kx_B 1740 which isthe complement of the Kx signal. Kx and Kx_B may be generated from adelay element having differential outputs as shown in FIG. 16A or 16B.Differential pair 1820 and 1830 receive the Ky 1710 phase vector and theKy_B 1750 complementary phase vector. The phase interpolator functionsas a weighted integrator using capacitors C1 1760 and C2 1770 andcoincidence detector 1860. If Ictl 1720 is set at a maximum value andIctl_B 1730 is zero then the output signal PIout 1870 is in phase withthe Kx clock but delayed by a stage delay through the interpolator. IfIctl_B 1730 is set a maximum value and Ictl 1720 is zero then the outputsignal is in phase with the Ky clock but delayed by a stage delay. Byadjusting the values of adjustable currents 1720 and 1730 any delaybetween Kx and Ky may be achieved.

[0057] The operation of loop 500 in FIG. 6 is as follows. Phase detector590 determines what the difference in phase, if any, is between theInput Clk 650 and FdBkClk 600. This difference is then processed bycontrol circuit 570 to select a pair of phase vectors via selectioncircuitry 510. The chosen pair of vectors is that pair between which thephase of Input Clk 650 lies, after accounting for fixed delays inherentin circuits in the path of the FdBkClk signal such as the phaseselector, phase interpolator, adjustable delay section and clock buffer.An example of a pair of vectors meeting this requirement is shown inFIG. 14, in which the Input Clk is shown between the 90 degree and 180degree vectors and at a delay of alpha degrees from the 180 degreevector. If the starting pair of vectors is not the correct pair then thecontrol circuit steps through the pairs of vectors one step at a timeuntil the correct pair is discovered. FIG. 15 depicts a circumstance inwhich the stepping of several phase vectors must occur if loop 500starts in the 0 degree state before the correct pair is discovered. Whenthe first pair of vectors, 0 and 45 degrees, is selected, the phaseinterpolator 560 is adjusted so that the phase interpolator output 615is in phase with the 45 degree vector. While in this condition the 0degree vector is replaced with the 90 degree vector by the controlcircuit and selection circuitry. Next, the phase interpolator isadjusted to produce an output in phase with the 90 degree vector and the45 degree vector is replaced with the 135 degree vector. The phaseinterpolator is then adjusted to produce an output in phase with the 135degree vector. Finally, the control circuit replaces the 90 degreevector with the 180 degree vector. Thus, while this stepping occursphase interpolator generates an output clock 615 which is in phase withone of the selected vectors, in particular, the one that will not beswitched in selecting a new pair of vectors. The constraint that theinterpolator generate the output clock in phase with the non-switchedvector prevents the output clock from glitching during the steppingprocess. When the correct pair of vectors is determined by the loop thenthe phase interpolator is allowed to be adjusted by PhAdj signal 550 toprecisely align the delayed output FdBkClk 600 to the phase of the InputClock 650, which is at some phase, alpha degrees, (FIG. 14) from one ofthe selected phase vectors. When this occurs the loop is locked. FdBkClk600 is delayed by at least one unit delay from adjustable delay section610, the unit delay being precisely a delay between the any two adjacentphase vectors 430 from the first loop because it is adjusted by the sameDlyAdj 440 signal of the first loop. Thus, if the phase vectors from thefirst loop differ from each other by 90 degrees, then the unit delay is90 degrees and the FdlkClk is delayed 90 degrees from the output of thephase interpolator 615, assuming one delay element in block 610. FIG. 14shows this condition.

[0058] It will be noted that not only is a unit delay included in thefeedback path of the second loop but so are the clock buffer and otherfixed delays inherent in the phase selector and phase interpolator.Clock buffers 620 and 630 are matched buffers having the same physicalconstruction. FdBkClk is thus delayed by an amount equal to a unit delayand a clock buffer delay plus the other fixed delays from the phaseselector and phase interpolator. However, because the Output Clock 640is delayed by the same amount of fixed delays, the clock buffer delaysand fixed delays cancel and the difference between the Output Clk 640and the Input Clock 640 is only the unit delay.

[0059] It should be noted that adjustable delay section 610 couldcomprise an integer multiple of unit delays, in which case the delaybetween the Input Clk 650 and Output Clk 640 would then be the integermultiple of unit delays. For example, if the multiple of the unit delayis 3 and the value of the unit delay 10 degrees then the Output Clkwould lead the Input Clk by 30 degrees. If the multiple of the unitdelay is zero, then the Input Clk and Output Clk would be in phase.

[0060]FIG. 7 is an alternate embodiment showing adjustable delay section612 in the path of the Output Clk 640. This section has the sameimplementation as the section in the path of the FdBkClk 600 andprovides a way for the Output Clk signal 640 to not only lead the InputClk in phase but to lag it in phase. This latter condition occurs whenthe adjustable delay section 612 comprises a larger multiple of unitdelays than adjustable delay section 610. Adjustable delay sections 612and 610 may be implemented in a fashion similar to section, 206 in FIG.4 in order to insure that phase errors due to loading differences areminimized. The delay circuits shown in FIGS. 16A and 16B are suitablefor implementing an adjustable delay element employed in the adjustabledelay section 610 or 612. FIG. 7 also shows that buffers 620 and 630 maybe implemented as duty cycle correcting amplifiers with the aid of dutycycle correction circuit 670. Buffers 620 and 630 may be implementedaccording to the circuitry shown in 19A and duty cycle correctioncircuit 670 may be implemented as shown in FIG. 19B. Finally, FIG. 7shows three more inputs, Fast 575, Test 585 and ExtIn 595, to thecontrol circuit 570. In one embodiment Fast signal 575 is used to alterthe control circuit so that the loop can lock more quickly by takinglarger phase adjustments toward the lock condition. In an embodiment inwhich the control circuit 570 is implemented as a counter, the Pastsignal 575 can cause the counter to count by a multiple of the smalleststep between counts. The Test signal 585 is used to allow the controlcircuit to be under the control of external signal ExtIn 595 rather thanPhDiff 580 derived from the loop. This allows loop properties to betested more easily.

[0061]FIG. 8 shows one embodiment of adjustable delay section 612. Block612 comprises a buffer 702, similar to 202 in FIG. 4, an adjustabledelay element 710 similar to adjustable delay element 210 in FIG. 4, andan output buffer 712 similar to the 212 buffer in FIG. 4. FIG. 9 showsan embodiment of adjustable delay section 610. This figure is similar toFIG. 8 but has more adjustable delay elements, but is still buffered atthe front of the chain and has an additional delay element at the end ofthe chain. The adjustable delay sections in both FIG. 8 and FIG. 9 arecontrolled from an external delay adjust signal such as 441 as shown inFIG. 7, such that the setting produces a delay equal to the delaybetween phase vectors. If the adjustable delay sections are implementedin this fashion, loading differences are kept to a minimum and only thedesired phase difference between signal 617 and 618 is generated. As maybe easily seen it is not necessary that adjustable delay sections 610and 612 be implemented as two separate and distinct sections. It isconvenient in some embodiments to derive 617 and 618 from the samesection 625 as shown in FIG. 7 and 10. The delay adjust signal 441 inFIG. 7 is buffered by buffer 442, in some embodiments, to isolate theloading effects of sections 610 and 612 from section 420.

[0062]FIG. 20 discloses circuitry for biasing the predetermined phaserelationship between the input clock and the output clock with a fixedoffset. The fixed offset is necessary when system requirements dictatethat the predetermined phase relationship be altered by an amount thatis smaller than is available from a unit a delay, for example a onedegree phase shift. This fine tuning or trimming is accomplished by theTrimAdj signal 2300 which is combined with the DlyAdj signal 441 in FIG.7. The TrimAdj signal 2300 adds a small amount of adjustment current tothe adjustable delay sections 610 and 612. This causes the delayelements in those sections to have a delay that is slightly smaller orlarger than the unit delay provided by the delay adjustment signal fromthe loop which generates the phase vectors. For example, if the delayelements in 610 and 612 are increased by one degree and the unit delayis 90 degrees than each delay element has a delay of 91 degrees. Becausethe delay between the input clock and the output clock is the differencein delay between the path of the output clock and the path of thefeedback clock, the output clock is now 91 degrees ahead of the inputclock. In FIG. 20, the TrimAdj signal 2300 is derived from DAC 2310 andtrim word storage 2320. Trim word storage in some embodiments is a setof fuses or other permanent storage for holding a digital code TW<t:0>2330 for setting the trim delay. DAC 2310 converts the trim word 2330 toan analog signal such as a current for controlling the delay elements insections 610 and 612.

[0063]FIG. 21 is a circuit diagram of a phase detector circuit whichcould be used for the phase detector of FIGS. 2, 3, 4, 6 and 7. A clockinput 2530 is shown, and data input 2540 would correspond to thefeedback clock or phase vector. Output 3000 is the phase differencesignal provided to the control circuit. The phase detector isimplemented as three blocks 2500, 2510, and 2520 connected in flip-flopfashion using NAND gates 2550, 2560, 2570, 2580, 2590, and 2595.

[0064]FIG. 22 shows a system application for the delay locked loops ofthe present invention. In the case shown, master device 3100communicates with slave device 3110 or slave device 3120. Slave devices3110 or 3120 may communicate with master device 3100 but not with eachother. The system operates from a pair of clocks generated fromoscillator 3170 which generates CTM (Clock To Master) 3140 and CFM(Clock From Master) 3130. CTM travels in the direction from the slavedevice to the master device and is used for transmitting data to themaster on data bus 3150. In the master, CTM is looped back to generateCFM which travels in the direction from master to slave device and isused for transmitting data from the master to the slave device. Eachdevice, master or slave, has a data receiver Rcvr 3180 and a datatransmitter Txmtr 3190 for receiving and sending data respectively. TheRcvr 3180 uses a signal rclk 3220 to receive the data from the data Busand Txmtr 3190 uses tclk 3230 to transmit the data onto the data bus.Signals rclk and tclk are generated from a pair of delay locked loops3200 and 3205 in the slave and from a single delay locked loop 3235 inthe master, because the master makes no distinction between CTM and CFM.

[0065] In FIG. 22 DLLR 3210 is the delay locked loop for generating thephase vectors and is called the reference loop. Each device uses asingle DLLR loop. DLLF 3200 is the delay locked loop for generating apredetermined phase relationship between the input clock and the outputclock. The DLLF 3200 loop is used to generate a 90 degree phaserelationship between CTM and tclk, because data is always transmitted inquadrature to the receive clock. The DLLF 3205 is used to generate azero degree phase relationship between CFM and rclk. Thus, when a slavesends data to the master, the data changes occur 90 degrees out of phasewith the CTM clock, the clock traveling toward the master. The masterreceives the clock CTM and generates the rclk signal for operating itsreceiver. Signal rclk in the master is in a 0 degree phase relationshipwith CTM so that the data is sampled when it is not changing. Similarly,when the master sends data to a slave, it clocks its transmitterchanging the data on the data bus with tclk which is in a 90 degreephase relationship with the CFM. A slave 3110 receiving the data in itsreceiver 3180 operates its receiver using rclk which has a 0 degreephase relationship with the CFM. Thus, the receiver will sample the datawhen it is not changing. In this manner, data may be transmitted usingboth edges of the CTM or CFM clocks and safely sampled in the receiver.

[0066] In one embodiment, the master of FIG. 22 is an intelligentdevice, such as a microprocessor, an application specific integratedcircuit (ASIC), a memory controller, or a graphics engine. The slavedevices may be DRAMs, SRAMs, ROMs, EPROMs, flash memories, or othermemory devices.

[0067] In the foregoing specification the invention has been describedwith reference to specific exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of theinvention. The specification and drawings are, accordingly, to beregarded in an illustrative rather than restrictive sense.

What is claimed is:
 1. A method for producing a set of phase vectors,the method comprising the steps of: producing a set of phase vectorsfrom a set of delay producing elements coupled in series to form achain, the first delay in the chain receiving a chain-input clock, thechain-input clock coupled to an input clock, wherein any two adjacentphase vectors are separated by an unit delay and all unit delays areequal; and adjusting the delays between phase vectors such that aselected phase vector is in a predetermined phase relationship with theinput clock, wherein the set of phase vectors spans a predetermineddegree of phase shift of the input clock.
 2. The method of claim 1,wherein the predetermined degree of phase shift of the input clockspanned by the phase vectors is 360 degrees.
 3. The method of claim 1,wherein the predetermined degree of phase shift of the input clockspanned by the phase vectors is 180 degrees.
 4. The method of claim 1,wherein the predetermined phase relationship between the input clock andthe last phase vector is 180 degrees.
 5. The method of claim 1, furthercomprising the step of storing the current adjustment of the delays inthe chain, wherein the predetermined phase relationship between theinput clock and the selected phase vector and the predetermined degreeof phase shift of the input clock are preserved during a period of timewhen the clock source is not present.
 6. The method of claim 1, whereinthe step of adjusting the delays between the vectors includes the stepof: detecting the deviation from the predetermined phase relationshipbetween the input clock and the selected phase vector.
 7. The method ofclaim 6, further comprising the step of filtering the detected deviationfrom the predetermined phase relationship to reduce loop jitter.
 8. Themethod of claim 1, wherein the chain-input clock and the outputs of eachdelay in the chain are buffered to produce the input clock and the setof phase vectors, respectively.
 9. The method of claim 1, wherein adelay element is coupled to the end of the chain so that all phasevectors produced by the chain have the same loading characteristics. 10.The method of claim 1, wherein the chain-input clock is coupled througha buffer to a clock source.
 11. The method of claim 10, wherein thebuffer is a duty cycle correcting amplifier.
 12. A method for generatinga predetermined phase relationship between an input clock and an outputclock, the method comprising the steps of: selecting a pair of phasevectors from a set of phase vectors, each vector separated in time froman adjacent vector by an unit delay; producing the output clock from aninterpolator that receives the selected pair of phase vectors; delayingthe output clock from the interpolator by a delay equal to a multiple ofthe unit delay to produce a feedback clock; adjusting the selection of apair of phase vectors received by the interpolator so that the phase ofthe input clock lies between the selected pair of phase vectors;detecting the difference in phase between the input clock and thefeedback clock; interpolating between selected pair of vectors so thatthe feedback clock is in phase with the input clock based on thedetected phase difference between the input clock and the feedbackclock; and wherein the output clock from the interpolator has thepredetermined phase relationship with the input clock, when the feedbackclock is in phase with the input clock, the predetermined phaserelationship being a multiple of the unit delay.
 13. The method of claim12, wherein the step of detecting the difference in phase includes thestep of filtering the detected phase difference between the input clockand the feedback clock.
 14. The method of claim 12, further comprisingthe step of storing the current selection of phase vectors and thecurrent adjustment of the interpolator, wherein the current selection ofphase vectors and the current adjustment of the interpolator arepreserved during a period of time when the input clock not is notpresent or the set of phase vectors is not present.
 15. The method ofclaim 12, wherein the multiple of the unit delay includes zero.
 16. Themethod of claim 12, further comprising the step of delaying the outputclock from the interpolator by a delay equal to a multiple of the unitdelay to produce the output clock, wherein the output clock has apredetermined phase relationship with the input clock, the predeterminedphase relationship being a multiple of the unit delay.
 17. The method ofclaim 16, wherein the output clock may lead or lag the input clock by amultiple of the unit delay.
 18. The method of claim 12, wherein theoutput clock from the interpolator is buffered with a first clock bufferto produce the output clock; and wherein the feedback clock is bufferedwith a second clock buffer to produce the feedback clock, the first andsecond clock buffers having substantially the same delay and the outputclock having a predetermined phase relationship with the input clock,the predetermined phase relationship being a multiple of the unit delay.19. Circuitry for producing a set of phase vectors, the circuitrycomprising: at least two adjustable delay elements each having a delayadjust signal, the delay elements coupled in series to form a chain forproducing a set of phase vectors, wherein at least one phase vector isproduced at the output of each delay element and wherein the first delayelement in the chain receives a chain-input clock, the chain-input clockcoupled to an input clock; and a delay adjusting circuit receiving theinput clock and a selected phase vector, the delay adjusting circuit foradjusting the delays between the phase vectors with the delay adjustsignal such that the input clock is in the predetermined phaserelationship with the selected phase vector and the set of phase vectorsspans a predetermined degree of phase shift of the input clock.
 20. Thecircuitry of claim 19, wherein the predetermined degree of phase shiftof the input clock spanned by the phase vectors is 360 degrees.
 21. Thecircuitry of claim 19, wherein the predetermined degree of phase shiftof the input clock spanned by the phase vectors is 180 degrees.
 22. Thecircuitry of claim 19, wherein the predetermined phase relationshipbetween the input clock and the last phase vector is 180 degrees. 23.The circuitry of claim 19, further comprising: a set of buffers eachcoupled to the output of a delay element in the chain, the set ofbuffers for producing a set of phase vectors at the output of the set ofbuffers; and a clock buffer having an input connected to the chain-inputclock, the clock buffer for producing the clock input, wherein the setof buffers and the clock buffer have substantially the same delay. 24.The circuitry of claim 19, wherein a delay element is added to thechain, the delay element receiving the last phase vector in the chain sothat all phase vectors produced by the chain have the same loadingcharacteristics.
 25. The circuitry of claim 19, wherein the delayadjusting circuit comprises: a phase detector receiving the input clockand the last phase vector, the phase detector for determining whetherthe input clock is in a predetermined phase relationship with the lastphase vector and for producing a phase detector output signal based onthe difference from the predetermined phase relationship between theinput clock and last phase vector; and a control circuit receiving thephase detector output signal and for generating the delay adjust signalbased on the phase detector output signal.
 26. The circuitry of claim25, wherein the control circuit includes a digital storage circuithaving state information for representing the current delay adjustmentof the loop.
 27. The circuitry of claim 26, wherein the stateinformation of the digital storage circuit is preserved when the clocksource is not present.
 28. The circuitry of claim 25, wherein thecontrol circuit comprises: a counter circuit receiving the phasedetector output signal and generating a digital count based on the phasedetector output signal; and a digital to analog converter receiving thedigital count and generating the delay adjust signal, wherein the delayadjust signal is an analog signal proportional to the digital count. 29.The circuitry of claim 25, wherein the control circuit comprises: afilter receiving the phase detector output signal and generating afiltered phase detector output signal for reducing loop jitter; acounter circuit the counter circuit receiving the filtered phasedetector output signal and generating a digital count based on the phasedetector output signal; and a digital to analog converter receiving thedigital count and generating the delay adjust signal, wherein the delayadjust signal is an analog signal proportional to the digital count. 30.The circuitry of claim 29, wherein the filter is a digital filter. 31.The circuitry of claim 25, further comprising: a duty cycle correctingamplifier having an input coupled to a clock source, the duty cyclecorrecting amplifier generating the chain-input clock; and a duty cyclecorrecting circuit receiving the chain-input clock and adjusting theduty cycle correcting amplifier such that the chain-input clock has aduty cycle substantially close to 50%.
 32. Circuitry for generating apredetermined phase relationship between a pair of clocks, the circuitcomprising: selection circuitry having as inputs a set of phase vectorsand a selection control signal, each vector separated in time from anadjacent vector by an unit delay, the selection circuitry for selectinga pair of phase vectors from the set; a phase interpolator circuitreceiving the selected pair of phase vectors and a phase adjust signaland generating a phase interpolator output clock, the phase interpolatorfor adjusting the phase of phase interpolator clock, wherein the outputclock is coupled to the phase interpolator output clock; at least onefeedback delay element coupled to the phase interpolator output clock toproduce a first delayed clock, the feedback delay element delaying thefirst delayed clock from the phase interpolator output clock by anamount equal to a multiple of the unit delay, wherein a feedback clockis coupled to the first delayed clock; and a phase adjusting circuitreceiving the input clock and the feedback clock, wherein the phaseadjusting circuit produces the selection control signal for adjustingthe selection of a pair of phase vectors produced by the selectioncircuitry so that the phase of the input clock lies between the selectedpair of phase vectors and wherein the phase adjusting circuit producesthe phase adjust signal for adjusting the phase interpolator so that thefeedback clock is in phase with the input clock, wherein the outputclock has the predetermined phase relationship with the input clock,when the feedback clock is in phase with the input clock, thepredetermined phase relationship being a multiple of the unit delay. 33.The circuitry of claim 32, wherein the multiple of the unit delayincludes zero.
 34. The circuitry of claim 32, further comprising: atleast one output delay element coupled to the phase interpolator outputclock to produce the output clock; and wherein the output delay elementdelays the output clock delayed by an amount equal to a multiple of theunit delay and wherein the output clock has a predetermined phaserelationship with the input clock, the predetermined phase relationshipbeing a multiple of the unit delay.
 35. The circuitry of claim 34,wherein the output clock may lead or lag the input clock by a multipleof the unit delay.
 36. The circuitry of claim 32, wherein the outputclock from the interpolator is buffered with a first clock buffer toproduce the output clock and wherein the feedback clock is buffered witha second clock buffer to produce the feedback clock, the first andsecond clock buffers having substantially the same delay and the outputclock having a predetermined phase relationship with the input clock,the predetermined phase relationship being a multiple of the unit delay.37. The circuitry of claim 32, wherein the phase adjusting circuitcomprises: a phase detector receiving the input clock and the feedbackclock, the phase detector for determining whether the feedback clock isin phase with the input clock and for producing a phase detector outputbased on the difference in phase between the feedback clock and theinput clock; and a control circuit receiving the phase detector outputsignal, the control circuit producing the selection control signalfor,adjusting the selection of a pair of phase vectors generated by theselection circuitry and producing the phase adjust signal for adjustingthe phase interpolator.
 38. The circuitry of claim 37, wherein thecontrol circuit includes a digital storage circuit having stateinformation for representing the current selection of phase vectors andthe adjustment of the phase interpolator.
 39. The circuitry of claim 38,wherein the state information of the digital storage circuit ispreserved when the input clock not is not present or the set of phasevectors is not present.
 40. The circuitry of claim 37, wherein thecontrol circuit includes: a counter circuit receiving the phase detectoroutput signal and generating a digital count based on the phase detectoroutput signal; and a digital to analog converter receiving the digitalcount and generating the phase adjust signal, wherein the phase adjustsignal is an analog signal proportional to the digital count.
 41. Thecircuitry of claim 37, wherein the control circuit includes: a filterreceiving the phase detector output signal and generating a filteredphase detector output signal for reducing loop jitter; a counter circuitreceiving the filtered phase detector output signal and generating adigital count based on the phase detector output signal; and adigital-to-analog converter receiving the digital count and generatingthe phase adjust signal, wherein the phase adjust signal is an analogsignal proportional to the digital count.
 42. The circuitry of claim 41,wherein the filter is a digital filter.
 43. The circuitry of claim 32,further comprising: a first duty cycle correcting amplifier receivingthe first delayed clock, the first duty cycle correcting amplifiergenerating the feedback clock; a second duty cycle correcting amplifierreceiving the phase interpolator output clock, the second duty cyclecorrecting amplifier generating the output clock; and a duty cyclecorrecting circuit receiving the feedback clock and adjusting the firstand second duty cycle correcting amplifiers such that the feedback clockand output clock have substantially the same duty cycle, wherein theduty cycle is substantially close to 50%.
 44. A method for generating apredetermined phase relationship between a pair of clocks, the methodcomprising the steps of: operating a first delay locked loop circuitryto generate a set of phase vectors from an input clock, wherein any twoadjacent phase vectors are separated by an unit delay and all unitdelays are equal and wherein the set of phase vectors spans apredetermined degree of phase shift of the input clock, when the firstloop is locked; and operating a second delay locked loop circuitry togenerate the predetermined phase relationship between the pair ofclocks, wherein a delayed version of the output clock is in phase to theinput clock, when the second loop is locked, the delayed version of theoutput clock being a multiple of the unit delay between the phasevectors generated from the first loop and the unit delay being derivedfrom the first delayed locked loop.
 45. A memory system comprising: acontroller; a least one memory circuit; a data bus coupling saidcontroller to said at least one memory circuit; a data transmitter anddata receiver circuit in at least one of said controller and said onememory circuit, at least one of said data transmitter and data receiverbeing coupled to clock circuitry for producing a set of phase vectors,said clock circuitry including at least two adjustable delay elementseach having a delay adjust signal, the delay elements coupled in seriesto form a chain for producing a set of phase vectors, wherein at leastone phase vector is produced at the output of each delay element andwherein the first delay element in the chain receives a chain-inputclock, the chain-input clock coupled to an input clock; and a delayadjusting circuit receiving the input clock and a selected phase vector,the delay adjusting circuit for adjusting the delays between the phasevectors with the delay adjust signal such that the input clock is in thepredetermined phase relationship with the selected phase vector and theset of phase vectors spans a predetermined degree of phase shift of theinput clock.